IBM has unveiled a novel chip architecture, designated NanoStack, which it claims could enable manufacturers to pack 100 billion transistors onto a silicon die the size of a fingernail. This design, equivalent to approximately 0.7 nanometres, would represent the industry's first sub-1nm technology, though commercial production remains several years distant. In tests, the prototype reportedly delivered a 50% improvement in performance and a 70% reduction in energy consumption relative to IBM's own 2nm chip. This represented a similar leap to that announced for the earlier node in 2021. Such advances underscore the relentless pursuit of miniaturisationminiaturisation/ˌmɪnɪətʃəraɪˈzeɪʃən/L3微型化；将物体或系统缩小到极小尺寸的过程the process of making something very small, especially electronic components or devices, a trajectorytrajectory/trəˈdʒɛktəri/L3轨迹；发展路径或趋势the path or course of development that something follows over time that has historically followed Moore's Law, though sustaining that pace grows increasingly arduousarduous/ˈɑːrdʒuəs/L3艰巨的；需要大量努力和耐力的involving great effort, difficulty, or hardship; strenuous. The breakthrough arrives amid intensifying competition in semiconductor manufacturing, where IBM, though no longer a fabricator, licenses its designs to partners.
Transistors, the fundamental building blocks of chips, underpin the computational power of everything from smartphones to data centres, which now drive generative AI and streaming services. IBM's approach, rather than merely shrinking transistors horizontally, involves stacking them vertically in layered sheets—a technique likened to constructing a high-rise block of flats. Professor Alan Woodward of Surrey University compared IBM's NanoStack to a 100-storey skyscraper, whereas rival efforts from Samsung and Intel resemble 30-50 storey buildings. This three-dimensional design aims to extend Moore's Law, which has seen transistor counts double approximately every two years, by circumventingcircumventing/ˌsɜːrkəmˈvɛntɪŋ/L3规避；绕过（障碍或限制）finding a way to overcome an obstacle or rule, often by clever or indirect means the physical limitations of planar scaling. Yet the transition to vertical architectures introduces formidable engineering challenges.
Chief among these challenges is heat dissipation, as transistors generate significant thermal energy during operation, and heat rises, potentially compromising performance in densely packed stacks. Additionally, excessively thin inter-layer gaps can impede the switching off of transistors, leading to functional failures. Jay Gambetta, director of IBM Research, described the NanoStack architecture as a 'landmark moment,' though industry observers remain cautious about the timeline to volume production. Notwithstanding the technical hurdles, IBM's proposal is arguably the most ambitious among its peers, positioning the company as a pivotalpivotal/ˈpɪvətl/L3关键的；起中心作用的of crucial importance in relation to the development or success of something force in semiconductor innovation despite its shift away from manufacturing.
